1. Field of the Invention
This invention relates to an output driver, and more particularly to a pseudo-ECL output driver circuit with improved speed performance using a closed loop circuit to derive a regulated current and an open loop circuit to rapidly switch a replica of that current through an output of the output circuit driver.
2. Description of the Relevant Art
Emitter-coupled logic ("ECL") circuits are advantageously used in high performance computer equipment in part because of the speed provided by ECL technology. Many conventional processor and memory chips are currently fabricated using complementary metal oxide semiconductor (CMOS) technology mostly due to the relatively low power dissipation and high density afforded by CMOS. In order to combine CMOS and ECL chips in the same system, the CMOS devices may be tailored to provide ECL-level voltage outputs. CMOS circuits that produce outputs at ECL levels may be referred to as pseudo-ECL (or "PECL") circuits.
Integrated circuit devices which have outputs for driving ECL-based chips preferably output precisely controlled voltage levels. This is because the ECL transistors should not be driven to saturation since speed is obtained by operating the transistors in a non-saturated mode. For example, conventional ECL input/output levels may be at (e.g., V.sub.DD -0.86 volts and V.sub.DD -1.81 volts) for binary logic levels "1" and "0," respectively. Pseudo-ECL circuits should therefore operate within the close constraints of conventional operating voltage levels (i.e., produce voltage levels that do not vary from the ECL input specification). CMOS circuits are usually driven rail-to-rail (full voltage supply levels) to reduce power dissipation. In pseudo-ECL application, provisions should be made to control the output voltage levels to values less than full rail-to-rail since the intent is to apply the output to the closely held ECL voltage range.
One example of a conventional MOS circuit 10 used to drive ECL-type voltage levels is shown in FIG. 1. Circuit 10 may therefore be considered a pseudo-ECL driver having driver transistors 12 with resistor loads 14. Current through transistors 12a and 12b can be controlled with differential input signals In. A current source 16 can be connected in series between transistors 12 and ground. A source-follower circuit 18 may be used to modulate current through a resistor 20 connected between the driver output Vout and a reference terminal voltage Vterm.
The reference terminal voltage is generally fixed to a pre-defined amount, preferably near the midscale between the logic "1" ECL level and the logic "0" ECL level. For example, if logic ECL levels "1" and "0" are V.sub.DD -0.86 and V.sub.DD -1.81, then Vterm is approximately V.sub.DD -1.335.
Resistor values 20 and the reference terminal Vterm may be applied on a substrate altogether separate from the substrate containing circuit 10 or, in the alternative, can be contained on the same substrate. Regardless of its configuration, it is desired that the reference terminal voltage be substantially fixed at a pre-defined amount so that the ECL voltage levels upon the output node Vout is derived solely from the current passing through resistor 20. Given a relatively constant resistor value for resistor 20, the high and low logic levels of ECL are thereby dependent upon the current through resistor 20. This assumes a relatively controlled current value to ensure proper margins are maintained for the ECL output levels. Unfortunately, close control of current through resistors 20 cannot be easily obtained.
In the example shown in FIG. 1, the output level produced at Vout will change with variations in the fabrication process used to manufacture circuit 10. For example, slight changes in the threshold voltages of transistors 12, or of the transistors within the source follower circuit 18, will cause corresponding changes in the current through resistor 20. Threshold changes may be the result of, for example, ion implant skew, gate oxide degradation, etc. Likewise, changes in the sheet resistivity or resistor length and width will cause a change in the resistance value of resistors 14. This may result in a change in the gate-to-source voltage applied to the source follower thereby varying current through resistor 20.
Circuit 10 suffers from a speed limitation in addition to it experiencing inappropriate variations in output voltage levels from the desired ECL high and low values. Circuit 10 depicts an open loop configuration, whereby a feedback from the output to the input is "open". Absent feedback, open loop circuits generally operate faster than closed loop circuits having feedback. However, the open loop configuration of circuit 10 nonetheless suffers speed limitations due primarily to the gate capacitance of the source follower transistors and secondarily to the drain parasitic capacitance of the driver transistors. Resistors 14 in conjunction with the capacitance on transistors 12 and device 18 establish an internal RC time constant delay between the time in which a transistor 12 switches to a low resistance state and current appears through the respective resistor 20. It is believed that speed performance of circuit 10 is limited by the time it takes current to pass through resistors 14, followed by the time it takes the current through resistors 14 to charge the gate conductor of the source-follower transistor. This two-stage delay severely limits the open loop configuration shown in FIG. 1.
As an effort to eliminate the effective processing variations within a pseudo-ECL driver circuit, many conventional driver circuits employ a closed loop configuration. An example of one conventional closed-loop pseudo-ECL driver circuit 24 is shown in FIG. 2. Circuit 24 is considered a closed loop circuit in that the output voltage modulated by an output of a switching device is forwarded back to the input of that switching device. The switching device can, according to one example, be an operational amplifier ("opamp") 26. Opamp 26 produces an output based on the comparison between voltage levels forwarded to its inverting and non-inverting inputs. One input can be configured to receive a switching input. If the switching inputs are configured as differential inputs then, a pair of circuits 24 and opamps 26 may be required. However, in the single-ended configuration, a single opamp 26 is used to modulate a transistor 28 arranged similar to the source-follower transistor within device 18 of FIG. 1. Depending on the voltage level of switching input signal, current will either be sourced from the reference terminal voltage or sunk into the reference terminal voltage across resistor 30.
The closed-loop arrangement shown in FIG. 2 beneficially feeds back the output voltage from driver circuit 24 to the input of opamp 26. After the input signal has switched, and time thereafter has somewhat elapsed, Vout will settle to the same voltage as the input signal voltage Vol or Voh. Accordingly, the input signal voltage can be considered a reference voltage switched between the ECL high voltage level Voh and the ECL low voltage level Vol. While the feedback approach serves to correct the output voltage level to the appropriate reference voltage high or low values over time, time is nonetheless required in order for the output to settle to the regulated amount. Closed loop circuit 24 yields even slower operating speeds than the open loop circuit 10 of FIG. 1 due primarily to the output settling time being dependent on the closed loop bandwidth of the feedback system.
U.S. Pat. No. 5,089,723 (herein incorporated by reference) describes a pseudo-ECL driver circuit which uses a closed loop arrangement and establishes busses internally for two output levels used in driving the ECL voltage levels. To address the problem of opamp settling time, the feedback path set forth in Patent 723 includes a transistor which is either identical to, or, to conserve power, a scaled down equivalent to the driver transistor coupled to the output node of the pseudo-ECL driver.
Problems which appear prevalent in conventional MOS-based pseudo-ECL driver circuits are (i) their susceptibility to process variations which skew the ECL output level and/or (ii) their relatively slow presentment of that output level. It is therefore desirable to derive a pseudo-ECL driver circuit which can place, with minimal delay, a regulated ECL voltage level at the output of the driver. The desired improvement must deal with consistently offering a regulated, either positive or negative current, through the resistor linking the output terminal and the reference terminal voltage. The current must be regulated to present an ECL upper or lower voltage level, but without suffering any delay in producing the regulated current through the resistor after switching has occurred.